4 items across 4 digests
Researchers from Université Grenoble Alpes and CNRS identified side-channel attack vulnerabilities in 2.5D and 3D chiplet packaging systems. This security research highlights potential risks for advanced semiconductor architectures that could affect adoption rates and require additional security investments.
UC Riverside researchers published findings on ESD protection for chiplet-based 3D microsystems, addressing critical reliability challenges in advanced semiconductor packaging. This research is vital for technologists as chiplet architectures become essential for high-performance computing and AI applications where traditional monolithic designs reach physical limits.
yieldWerx has delivered implementation expertise for co-packaged photonics technology as the semiconductor industry faces unprecedented data intensity demands. This advancement enables higher performance through the integration of optical I/O and photonics with chiplets, addressing critical bandwidth limitations in data centers and high-performance computing.
Semiconductor industry faces 400% data surge requiring alternatives to silicon and electrical interconnects. This drives innovation in chiplet architecture and new materials, potentially increasing demand for advanced materials and rare earth elements.
DailySand